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᮪ 筮 .  ⨢ ᯮ RAMDAC-, ॣ
ࠢ, misc. register  .  ᯨ᮪ . vga.doc (vgabios.doc).


1. ATTRIBUTE CONTROLLER

       3C0h:  Attribute Controller: Address register
       bit 0-4  Address of data register to write to port 3C0h
		or read from port 3C1h (Reads only on VGA).
	     5  If set screen output is enabled and the palette can not be
		modified, if clear screen output is disabled and the palette
		can be modified.


	 Port 3C0h is special in that it is both address and data-write
	 register. Data reads happen from port 3C1h. An internal
	 flip-flop remembers whether it is currently acting as
	 address or data register.
	 Accesses to the attribute controller must be separated by
	 at least 250ns.
	 Reading port 3dAh will reset the flip-flop to address mode.


       3C0h index 0-Fh  (r/W): Attribute: Palette
	 bit 0  (EGA) Primary Blue
	     1  (EGA) Primary Green
	     2  (EGA) Primary Red
	     3  (EGA) Secondary Blue
	     4  (EGA) Secondary Green
	     5  (EGA) Secondary Red
	   0-5  (VGA) Index into the 256 color DAC table.
		      May be modified by 3C0h index 10h and 14h.

       3C0h index 10h (r/W): Attribute: Mode Control Register
	 bit 0  Graphics mode if set, Alphanumeric mode else.
	     1  Monochrome mode if set, color mode else.
	     2  9-bit wide characters if set.
		The 9th bit of characters C0h-DFh will be the same as
		the 8th bit. Otherwise it will be the background color.
	     3  If set Attribute bit 7 is blinking, else high intensity.
	     5  (VGA Only) If set the PEL panning register (3C0h index 13h)
			   is temporarily set to 0 from when the line
			   compare causes a wrap around until the next
			   vertical retrace when the register is automatically
			   reloaded with the old value, else the PEL
			   panning register ignores line compares.
	     6  (VGA Only) If set pixels are 8 bits wide.
			   Used in 256 color modes.
	     7  (VGA Only) If set bit 4-5 of the index into the DAC table
			   are taken from port 3C0h index 14h bit 0-1,
			   else the bits in the palette register are used.

       3C0h index 11h (r/W): Attribute: Overscan Color Register.
       bit 0-5  Color of screen border. Color is defined as in the
		palette registers.
       Note: The EGA requires the Overscan color to be 0 in high resolution
	     modes.

       3C0h index 12h (r/W): Attribute: Color Plane Enable Register
	 bit 0  Bit plane 0 is enabled if set.
	     1  Bit plane 1 is enabled if set.
	     2  Bit plane 2 is enabled if set.
	     3  Bit plane 3 is enabled if set.
	   4-5  Video Status MUX. Diagnostics use only.
		Two attribute bits appear on bits 4 and 5 of the Input
		Status Register 1 (3dAh).
		  Value       EGA            VGA
		    0      Red/Blue        Bit 2/Bit 0
		    1      Blue'/Green     Bit 5/Bit 4
		    2      Red'/Green'     Bit 3/Bit 1
		    3                      Bit 7/Bit 6

       3C0h index 13h (r/W): Attribute: Horizontal PEL Panning Register
       bit 0-3  Indicates number of pixels to shift the display left
		 Value  9bit textmode   256color mode   Other modes
		    0          1               0              0
		    1          2              n/a             1
		    2          3               1              2
		    3          4              n/a             3
		    4          5               2              4
		    5          6              n/a             5
		    6          7               3              6
		    7          8              n/a             7
		    8          0              n/a            n/a

       3C0h index 14h (r/W): Attribute: Color Select Register  (VGA Only)
       bit 0-1  If 3C0h index 10h bit 7 is set these 2 bits are used
		as bits 4-5 of the index into the DAC table.
	   2-3  These 2 bits are used as bit 6-7 of the index into the
		DAC table except in 256 color mode.

       Note: this register does not affect 256 color modes.


2.CRTC (3d4=color, 3b4=mono)

       3d4h index  0  (r/W): CRTC: Horizontal Total Register
       bit 0-7  (EGA) Horizontal Total Character Clocks-2
	   0-7  (VGA) Horizontal Total Character Clocks-5

       3d4h index  1  (r/W): CRTC: Horizontal Display End Register
       bit 0-7  Number of Character Clocks Displayed -1

       3d4h index  2  (r/W): CRTC: Start Horizontal Blanking Register
       bit 0-7  The count at which Horizontal Blanking starts

       3d4h index  3  (r/W): CRTC: End Horizontal Blanking Register
       bit 0-4  Horizontal Blanking ends when the last 5 (6 for VGA)
		bits of the character counter equals this field.
		(VGA) The sixth bit is found in port 3d4h index 5 bit 7.
	   5-6  Number of character clocks to delay start of display
		after Horizontal Total has been reached.
	     7  (VGA Only) Access to Vertical Retrace registers if set
			   If clear reads to 3d4h index 10h and 11h
			   access the Lightpen readback registers ??

       3d4h index  4  (r/W): CRTC: Start Horizontal Retrace Register
       bit 0-7  Horizontal Retrace starts when the Character Counter
		reaches this value.

       3d4h index  5  (r/W): CRTC: End Horizontal Retrace Register
       bit 0-4  Horizontal Retrace ends when the last 5 bits of the
		character counter equals this value.
	   5-6  Number of character clocks to delay start of display
		after Horizontal Retrace.
	     7  (EGA) Provides Smooth Scrolling in Odd/Even mode.
		      When set display starts from an odd byte.
	     7  (VGA) bit 5 of the End Horizontal Blanking count
		      (See 3d4h index 3 bit 0-4).

       3d4h index  6  (r/W): CRTC: Vertical Total Register
       bit 0-7  Lower 8 bits of the Vertical Total
		Bit 8 is found in 3d4h index 7 bit 0.
		(VGA) Bit 9 is found in 3d4h index 7 bit 5.
       Note: For the VGA this value is the number of scan lines in the display -2.

       3d4h index  7  (r/W): CRTC: Overflow Register
	 bit 0  Bit 8 of Vertical Total (3d4h index 6)
	     1  Bit 8 of Vertical Display End (3d4h index 12h)
	     2  Bit 8 of Vertical Retrace Start (3d4h index 10h)
	     3  Bit 8 of Start Vertical Blanking (3d4h index 15h)
	     4  Bit 8 of Line Compare Register (3d4h index 18h)
	     5  (VGA) Bit 9 of Vertical Total (3d4h index 6)
	     6  (VGA) Bit 9 of Vertical Display End (3d4h index 12h)
	     7  (VGA) Bit 9 of Vertical Retrace Start (3d4h index 10h)

       3d4h index  8  (r/W): CRTC: Preset Row Scan Register
       bit 0-4  Number of lines we have scrolled down in the first
		character row. Provides Smooth Vertical Scrolling.
	   5-6  (VGA Only) Number of bytes to skip at the start of
		scanline. Provides Smooth Horizontal Scrolling
		together with the Horizontal Panning Register
		(3C0h index 13h).

       3d4h index  9  (r/W): CRTC: Maximum Scan Line Register
       bit 0-4  Number of scan lines in a character row -1
	     5  (VGA) Bit 9 of Start Vertical Blanking
	     6  (VGA) Bit 9 of Line Compare Register
	     7  (VGA) Doubles each scan line if set.
		I.e displays 200 lines on a 400 display.

       3d4h index  Ah (r/W): CRTC: Cursor Start Register
       bit 0-4  First scanline of cursor within character.
	     5  (VGA) Turns Cursor off if set

       3d4h index  Bh (r/W): CRTC: Cursor End Register
       bit 0-4  Last scanline of cursor within character
	   5-6  Delay of cursor data in character clocks.

       3d4h index  Ch (r/W): CRTC: Start Address High Register
       bit 0-7  Upper 8 bits of the start address of the display buffer

       3d4h index  Dh (r/W): CRTC: Start Address Low Register
       bit 0-7  Lower 8 bits of the start address of the display buffer

       3d4h index  Eh (r/W): CRTC: Cursor Location High Register
       bit 0-7  Upper 8 bits of the address of the cursor

       3d4h index  Fh (r/W): CRTC: Cursor Location Low Register
       bit 0-7  Lower 8 bits of the address of the cursor

       3d4h index 10h (R): CRTC: Light Pen High Register     (EGA Only)
       bit 0-7  (EGA Only)  Upper 8 bits of the address of the
			    lightpen position.

       3d4h index 10h (r/W): CRTC: Vertical Retrace Start Register
       bit 0-7  Lower 8 bits of Vertical Retrace Start. Vertical Retrace
		starts when the line counter reaches this value.
		Bit 8 is found in 3d4h index 7 bit 2.
		(VGA Only) Bit 9 is found in 3d4h index 7 bit 7.

       3d4h index 11h (R): CRTC: Light Pen Low Register      (EGA Only)
       bit 0-7  (EGA Only)  Lower 8 bits of the address of the
			    lightpen position.

       3d4h index 11h (r/W): CRTC: Vertical Retrace End Register
       bit 0-3  Vertical Retrace ends when the last 4 bits of the
		line counter equals this value.
	     4  if clear Clears pending Vertical Interrupts.
	     5  Vertical Interrupts (IRQ 2) disabled if set.
		Can usually be left disabled, but some systems
		(including PS/2) require it to be enabled.
	     6  (VGA Only) If set selects 5 refresh cycles per
			   scanline rather than 3.
	     7  (VGA Only) Disables writing to registers 0-7 if set
		     3d4h index 7 bit 4 is not affected by this bit.

       3d4h index 12h (r/W): CRTC: Vertical Display End Register
       bit 0-7  Lower 8 bits of Vertical Display End. The display
		ends when the line counter reaches this value.
		Bit 8 is found in 3d4h index 7 bit 1.
		(VGA Only) Bit 9 is found in 3d4h index 7 bit 6.

       3d4h index 13h (r/W): CRTC: Offset register
       bit 0-7  Number of bytes in a scanline / K. Where K is 2 for
		byte mode, 4 for word mode and 8 for Double Word mode.

       3d4h index 14h (r/W): CRTC: Underline Location Register
       bit 0-4  Position of underline within Character cell.
	     5  (VGA Only) If set memory address is only changed
			   every fourth character clock.
	     6  (VGA Only) Double Word mode addressing if set

       3d4h index 15h (r/W): CRTC: Start Vertical Blank Register
       bit 0-7  Lower 8 bits of Vertical Blank Start. Vertical blanking
		starts when the line counter reaches this value.
		Bit 8 is found in 3d4h index 7 bit 3.

       3d4h index 16h (r/W): CRTC: End Vertical Blank Register
       bit 0-4  (EGA) Vertical blanking stops when the lower 5 bits
		      of the line counter equals this field.
	   0-6  (VGA) Vertical blanking stops when the lower 7 bits
		      of the line counter equals this field.

       3d4h index 17h (r/W): CRTC: Mode Control Register
	 bit 0  If clear use CGA compatible memory addressing system
		by substituting character row scan counter bit 0 for
		address bit 13, thus creating 2 banks for even and
		odd scan lines.
	     1  If clear use Hercules compatible memory addressing
		system by substituting character row scan counter bit 1 for
		address bit 14, thus creating 4 banks.
	     2  If set increase scan line counter only every second line.
	     3  If set increase memory address counter only every other
		character clock.
	     4  (EGA Only) If set disable the EGA output drivers. This bit
		is used for other purposes in some Super VGA chips.
	     5  When in Word Mode bit 15 is rotated to bit 0 if this bit
		is set else bit 13 is rotated into bit 0.
	     6  If clear system is in word mode. Addresses are rotated
		1 position up bringing either bit 13 or 15 into bit 0.
	     7  Clearing this bit will reset the display system
		until the bit is set again.

       3d4h index 18h (r/W): CRTC: Line Compare Register
       bit 0-7  Lower 8 bits of the Line Compare. When the Line counter
		  reaches this value, the display address wraps to 0.
		  Provides Split Screen facilities.
		  Bit 8 is found in 3d4h index 7 bit 4.
		  (VGA Only) Bit 9 is found in 3d4h index 9 bit 6.

3. SEQUENCER

       3C4h index  0  (r/W): Sequencer: Reset
	 bit 0  (EGA) Asynchronous Reset if clear
	     0  (VGA) Synchronous Reset just as bit 1
	     1  Synchronous Reset if clear

       3C4h index  1  (r/W): Sequencer: Clocking Mode
	 bit 0  If set character clocks are 8 dots wide, else 9.
	     1  (EGA Only) If set the CRTC uses 2/5 of the clock cycles, else 4/5.
	     2  If set loads video serializers every other character
		clock cycle, else every one.
	     3  If set the Dot Clock is Master Clock/2, else same as
		Master Clock (See 3C2h bit 2-3). (Doubles pixels).
	     4  (VGA Only) If set loads video serializers every fourth
			   character clock cycle, else every one.
	     5  (VGA Only) if set turns off screen and gives all memory
			   cycles to the CPU interface.

       3C4h index  2  (r/W): Sequencer: Map Mask Register
	 bit 0  Enable writes to plane 0 if set
	     1  Enable writes to plane 1 if set
	     2  Enable writes to plane 2 if set
	     3  Enable writes to plane 3 if set

       3C4h index  3  (r/W): Sequencer: Character Map Select Register
       bit 0-1  (EGA) Selects EGA Character Map (0..3) if bit 3 of
		      the character attribute is clear.
	   2-3  (EGA) Selects EGA Character Map (0..3) if bit 3 of
		      the character attribute is set.
	 0,1,4  (VGA) Selects VGA Character Map (0..7) if bit 3 of
		      the character attribute is clear.
	 2,3,5  (VGA) Selects VGA Character Map (0..7) if bit 3 of
		      the character attribute is set.

		  Character Maps are placed at:
		   Map no. (EGA/VGA)       Map no. (VGA)
		      0       0k              4      8k
		      1      16k              5     24k
		      2      32k              6     40k
		      3      48k              7     56k

       3C4h index  4  (r/W): Sequencer: Memory Mode Register
	 bit 0  Set if in an alphanumeric mode, clear in graphics modes.
	     1  Set if more than 64kbytes on the adapter.
	     2  Enables Odd/Even addressing mode if set.
		Odd/Even mode places all odd bytes in plane 1&3, and
		all even bytes in plane 0&2.
	     3  (VGA Only)  If set address bit 0-1 selects video memory
			    planes (256 color mode), rather than the
			    Map Mask and Read Map Select Registers.

